1. Field of the Invention
The invention generally relates to computer bus systems and in particular to computer bus systems incorporating buses configured in accordance with the Peripheral Component Interconnect (PCI) local bus specification.
2. Background
Computer systems employ a wide variety of peripheral components or input/output (I/O) devices. For example, a typical computer system usually contains a monitor, a keyboard, a mouse, a floppy drive, a network controller, a disk drive or an array of disk drives, and, optionally, a printer. High performance computer systems such as servers have more complex I/O device requirements.
Typically, a host processor of the computer system loads a software driver for each of the devices that the computer system is to support. The drivers are loaded into the memory of the system host processor and address space must be allocated to these devices. In addition, in operation, the devices generate interrupts that contend for the processing time of the host processor. System performance suffers dramatically with an increase in the number of I/O devices that the host processor has to support. In addition, there is a loss of bandwidth on the bus due to I/O device interaction from loss bus utilization time due to movement of data and control signals in operation.
An example of a host processor of a computer system connected to I/O devices through a component bus is defined by the PCI Local Bus Specification, Revision 2.0, published by the PCI Special Interest Group. During system initialization, the host processor loads a device driver for each PCI device on the PCI bus. During operation, the PCI bus is occupied each time a read or write transaction is occurring. The part of the host processor's processing time that is used in processing the interrupts generated by each PCI device is taken away from the total processing time of the host processor.
In high performance computer systems such as file and application servers, the time that a host processor spends processing I/O interrupts from PCI devices is considerable and drastically limits the time which the host processor can spend on other computing tasks. This problem is exacerbated as more devices are added to the PCI bus, such as through the use of a PCI-to-PCI bridge following PCI-to-PCI Bridge Architecture Specification, Revision 1.0, for example. As the number of PCI devices connected to the PCI bus increases by the use of the PCI-to-PCI bridge, the host processor spends more and more time dealing with I/O transactions and, therefore, has less time to perform other functions.
The parent of the present application describes one technique for reducing the burden on host processors and host processor system buses for processing signals, such as interrupt signals, generated by devices connected to a secondary PCI bus interface. More specifically, the parent application describes an arrangement wherein a secondary PCI bus is connected through a PCI-to-PCI bridge to a primary PCI bus. The primary PCI bus is connected through a host-to-PCI bridge to a host bus which interconnects one or more host microprocessors. Several devices may be connected to the secondary PCI bus. The PCI-to-PCI bridge is configured to define a private address space within the PCI address space to allow devices connected to the secondary PCI bus to communicate with each other without involving the primary PCI bus, the host-to-PCI bridge, the host bus and the host microprocessors.
Briefly, private address spaces are implemented by configuring a secondary PCI interface to recognize a private address space within the PCI address space. Ordinarily, a secondary PCI interface of the PCI-to-PCI bridge captures all transactions having addresses outside of a secondary address space portion of the PCI address space and forwards those transactions to the primary PCI bus. This is referred to herein as "inverse positive address decoding." To implement the private address space, inverse positive decoding is disabled for a portion of the primary PCI address space ordinarily subject to inverse positive decoding. The address range for which inverse positive decoding is disabled is the private address space. Any transactions within the private address space are therefore not captured by the secondary PCI interface and are not routed to the primary PCI bus. Rather, transactions within the private address space are allowed to be captured by other "peer" PCI devices connected to the secondary PCI bus. In this manner, bus transactions within the private address space are not visible to the host processors and do not burden the host processors or the host bus. Details of the implementation of private address spaces was set forth in the parent application and is provided herein as well.
Thus, the implementation of private address spaces within a secondary PCI bus allows devices connected to the secondary PCI bus to communicate with one another without burdening the primary PCI bus, the host bus or the host microprocessor. Private address spaces are primarily intended for use within "hierarchical" PCI bus configurations of the type described above wherein the secondary PCI bus is interconnected through a primary PCI bus to the host bus. Room for improvement, however, remains.
With private address spaces, it is possible, for one reason or another, that transactions defined within the private address space may not be claimed by any of the PCI devices connected to the secondary PCI bus. Since the transactions are within the private address space, the transactions are therefore also not captured by the secondary PCI interface. Accordingly, an error condition can occur. It would be desirable to provide an improved method for implementing a private address space wherein such error conditions are avoided.
Also, although private address spaces facilitate communication between a pair of peer PCI devices connected to the same secondary PCI bus, private address spaces are not necessarily helpful in facilitating communication between PCI devices connected to separate peer PCI buses. In other words, within an arrangement wherein two separate primary PCI buses are connected through respective host-to-PCI bridges to a single host bus, devices connected to the separate primary PCI buses cannot ordinarily communicate with one another without routing the transactions over the host bus thereby consuming host bus bandwidth and burdening the host processors. It would be desirable to provide an improved PCI bus system wherein transactions between PCI devices connected to peer PCI buses can be accommodated without requiring routing of transactions onto the host bus. It is to these ends that aspects of the present invention are drawn.